The invention relates to the field of single-chip embedded microprocessors having analog and digital electrical interfaces to external systems. More particularly, the invention relates to a novel processor core for pipelined execution of multiple independent or dependent concurrent threads, together with supervisory control for monitoring and controlling the processor thread state and access to other components.
“Multithreading” defines a microprocessor's capability to execute different parts of a system program (“threads”) simultaneously. Multithreading can be achieved with software or hardware systems. Multithreading with a single processor core can be achieved by dividing the execution time of the processor core so that separate threads execute in segmented time windows, by pipelining multiple concurrent threads, or by running multiple processors in parallel. A microprocessor preferably has the ability to execute a single instruction on multiple data sets (“SIMD”) and multiple instructions on multiple data sets (“MIMD”).
The field of embedded processors substantially differs from non-embedded processors because embedded processors require 1) low manufacturing cost, 2) low power consumption and low heat dissipation, 3) rigorous real time multi-task execution, and 4) on-chip integration of special purpose and input/output peripherals. Non-embedded processors for server and personal computers maximize processing power and processing throughput and view cost as a secondary consideration. In non-embedded processors, power consumption is less important because non-embedded processors are directly connected to utility power sources and have extensive fin, fan, or refrigeration systems to dissipate large quantities of heat expended during operation. Non-embedded systems typically have a more distributed architecture than embedded processors and have central processor or cluster of processors interconnected to various other input/output, display and storage devices and systems with high speed back-plane structures, local area networks, and telecommunication facilities. Non-embedded processor chip implementations are much more complex than embedded processors and typically contain millions of transistors instead of the several hundred thousand transistors typically used in embedded processors.
Within the field of embedded microprocessors, multitasking to service multiple input/output interfaces and other embedded programs is common. Conventional embedded processors have a single processor that executes one instruction or one task segment comprising a group of instructions. Interrupts allocate the available processor time across multiple competing application tasks. As each new task is prepared for execution in its allocated time segment, the application state or “context” of the last task executed is stored. Real time programs for conventional single processor systems are inherently difficult to design and are inefficient because of the continuous context swapping requirements for such systems.
Various multithread processor systems have been developed. U.S. Pat. No. 5,907,702 to Flynn et al. (1999) described a serial-thread execution system for decreasing thread switch latency in a multithread processor by executing an active thread on the primary instruction queue and by keeping a dormant thread in a secondary queue (with full context storage) for subsequent execution. U.S. Pat. No. 6,134,653 to Roy et al. (2000) described a processor architecture having three sets of general purpose registers to permit rapid context switching between serially-executing program threads. U.S. Pat. No. 5,404,469 to Chung et al. (1995) described a static interleaving technique wherein multiple functional units in a processor were allocated for the execution of an entire instruction from a particular thread in a fixed predetermined time slot in a repeating pattern of predetermined time slots. U.S. Pat. No. 5,546,593 (1996) and U.S. Pat. No. 6,105,127 (2000) to Kimura et al. described a processor architecture for executing multiple instruction streams simultaneously using parallel hardware execution streams and control and prioritization units for selecting and directing each thread to execute in a given stream at a given time.
U.S. Pat. No. 4,646,236 to Crockett et al. (1987) and U.S. Pat. No. 5,357,617 to Davis et al. (1994) described three-stage pipelines. Additionally, various approaches have been proposed to organize the execution of multiple concurrent program threads across multiple non-pipelined processors. U.S. Pat. No. 6,094,715 to Wilkinson et al. (2000), and U.S. Pat. No. 5,966,528 to Wilkinson et al. (1999), and U.S. Pat. No. 5,878,241 to Wilkinson et al. (1999), and U.S. Pat. No. 5,828,894 to Wilkinson et al. (1998), and U.S. Pat. No. 5,761,523 to Wilkinson et al. (1998), and U.S. Pat. No. 5,754,871 to Wilkinson et al. (1998) describe arrays of processors configurable for SIMD, MIMD or a combination of SIMD/MIMD operation. U.S. Pat. No. 5,734,921 to Dapp et al. (1998) describes a parallel array processor or matrix of such processors containing multiple processors that can operate in SIMD, MIMD or combined SIMD/MIMD modes of operation.
Hardware semaphores have been contemplated for memory addresses per U.S. Pat. No. 5,276,847 to Kohn (1994) and for more general system resources as shown in U.S. Pat. No. 6,101,569 to Miyamoto et al. (2000).
Various approaches have been proposed to supervise and control the execution of non-embedded multithread processors. U.S. Pat. No. 5,835,705 to Larsen et al. (1998) described a non-pipelined multithread processor system that counts events per thread and generates an interrupt in response to a count to initiate further action such as performance buffer overflow processing. U.S. Pat. No. 5,923,872 (1999) and U.S. Pat. No. 6,000,044 (1999) to Chrysos et al. described systems for providing samples of detailed state information and instructions in a multiple stage processor pipeline. A profile of such state information per instruction sampled was stored in internal profile registers and later analyzed in response to an interrupt condition or software polling. U.S. Pat. No. 6,018,759 to Doing et al. (2000) and U.S. Pat. No. 6,052,708 to Flynn et al. (2000) described non-pipelined multithreaded processor systems wherein a thread switch controller switched processor threads based upon results from a performance monitoring facility. U.S. Pat. No. 6,073,159 to Emer et al. (2000) described a technique for selecting a preferred thread from a plurality of threads within a simultaneous multithreaded execution computer system. U.S. Pat. No. 6,076,157 to Borkenhagen et al. (2000) described a system for switching between two or more threads of instructions capable of independent execution.
Although different systems have been proposed to provide efficient operation for embedded microprocessor applications, a need exists for a system having enhanced operating capabilities.